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PROJECTS

Project |01

 

Project |01  Line Following Robot : Freescale Cup

 

 

Project |02

 

Project |02 Tetris-2-D (Popular Game)

 

Implemented Tetris game in VHDL language. Interfaced Xilinx ISE digilent nexys-2 FPGA board with VGA (monitor), and keyboard. Designed state machine diagram. Wrote VHDL code for VGA unit, Keyboard control unit, and Tetris control module. Simulated each unit for proper functionality. Placed and routed the design using Xilinx ISE.

Project |03

 

Project |01 CMOS VLSI implementation of Alpha-Microprocessor-IVM 1.1 Model for Low Power Design

 

Implementation of an Alpha microprocessor (Illinois Verilog Model 1.1) for low power designed. Project developed in CMOS TSMC 0.18um technology using Cadence RTL Compiler and Synopsys VCS Simulator. IVM 1.1 Model is similar to Superscalar Hardware Speculation Dynamic Scheduling MIPS version 5 Model. Calculated Power, Area, and Performance of original IVM 1.1 model. Calculated performance by running different benchmarks. Modified Fetch Unit and Retire Unit of the original design to reduce the power and area. Calculated Area, Power and Performance of modified Architecture. Compared the Power, Performance and Area of both architectures.

Just a sample of my work. To see more or discuss possible work >>
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